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Configuration Devices for
(R)
SRAM-Based LUT Devices
Data Sheet
December 2002, ver. 12.2
Features

Serial device family for configuring APEXTM II, APEX 20K (including APEX 20K, APEX 20KC, and APEX 20KE), MercuryTM, ACEX(R) 1K, and FLEX(R) (FLEX 6000, FLEX 10KE, and FLEX 10KA) devices Easy-to-use 4-pin interface to APEX II, APEX 20K, Mercury, ACEX, and FLEX devices Low current during configuration and near-zero standby current 5.0-V and 3.3-V operation Software design support with the Altera(R) Quartus(R) II and MAX+PLUS(R) II development systems for Windows-based PCs as well as Sun SPARCstation, and HP 9000 Series 700/800 Programming support with Altera's Master Programming Unit (MPU) and programming hardware from Data I/O, BP Microsystems, and other manufacturers Available in compact plastic packages (see Figures 1 and 2) - 8-pin plastic dual in-line package (PDIP) - 20-pin plastic J-lead chip carrier (PLCC) package - 32-pin plastic thin quad flat pack (TQFP) package - 100-pin plastic thin quad flat pack (TQPF) package - 88-pin Ultra FineLine BGATM package EPC2 device has reprogrammable Flash configuration memory - 5.0-V and 3.3-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface - Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1 - ISP circuitry is compatible with IEEE Std. 1532 for EPC2 configuration device - Supports programming through Serial Vector Format Files (.svf), JamTM Standard Test and Programming Language (STAPL) Files (.jam), Jam STAPL Byte-Code Files (.jbc), and the MAX+PLUS II software via the MasterBlasterTM, ByteBlasterMVTM, or BitBlasterTM download cable - nINIT_CONF pin allows a JTAG instruction to initiate device configuration - Can be programmed with Programmer Object Files (.pof) for EPC1 and EPC1441 devices - Available in 20-pin PLCC and 32-pin TQFP packages
Altera Corporation
DS-EPROM-12.2
1
Configuration Devices for SRAM-based LUT Devices Data Sheet
EPC4, EPC8, and EPC16 configuration devices have reprogrammable Flash configuration memory with density up to 16,000,000 or 32,000,000 bits with compression feature in these devices.
f
For detailed information on configuration devices, refer to the Enhanced Configuration Devices (EPC4, EPC8, & EPC16) Data Sheet. Note (1)
VCC N.C. N.C. N.C.
26
Figure 1. EPC1, EPC1441, EPC1213, EPC1064, & EPC1064V Package Pin-Out Diagrams
DATA N.C. N.C.
32
31
30
29
28
27
N.C.
DATA VCC N.C. N.C. N.C.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
25 24 23 22 21 20 19 18 17 16
N.C. N.C. VCC N.C. N.C. N.C. N.C. N.C. N.C. N.C.
DCLK N.C.
DCLK
DATA DCLK OE nCS 1 2 3 4 8 7 6 5 VCC VCC nCASC (2) GND
3 4 5 6 7 8 9 nCS
2
1
20
19 18 17 16 15
VCC N.C. N.C. N.C. N.C.
N.C. N.C. N.C. OE N.C.
N.C. N.C. N.C. OE
10 GND
11 N.C.
12
14 13 N.C.
N.C.
N.C.
N.C.
N.C.
(2) nCASC
8-Pin PDIP EPC1 EPC1441 EPC1213 EPC1064 EPC1064V
Notes to Figure 1:
(1) (2)
20-Pin PLCC EPC1 EPC1441 EPC1213 EPC1064 EPC1064V
32-Pin TQFP EPC1441 EPC1064 EPC1064V
EPC1, EPC1441, EPC1213, and EPC1064 devices are one-time programmable devices. ISP programming is not available in these devices because they do not have JTAG pins. The nCASC pin is available on EPC1 and EPC1213 devices. On the EPC1064, EPC1064V, and EPC1441 devices, it is a reserved pin and should not be connected.
2
GND
Altera Corporation
N.C.
nCS
Configuration Devices for SRAM-Based LUT Devices Data Sheet
Figure 2. EPC2 Package Pin-Out Diagrams
DATA TDO TMS
25 24 23 22 21 20 19 18 9 10 11 12 13 14 17 15 16
VCC
TCK
N.C.
N.C.
N.C.
DATA VCC TDO TMS TCK
32 31 1 2 3 4 5 6 7 8
30 29 28
27 26
N.C.
N.C. VPP N.C. N.C. N.C. N.C. N.C. VPPSEL
DCLK VCCSEL
DCLK VCCSEL N.C. N.C. OE
4 5 6 7 8
3
2
1
20 19 18 17 16 15
VPP N.C. N.C. N.C. VPPSEL
N.C. N.C. N.C. OE N.C.
9 nCS
10 11 TDI GND
14 12 13 nINIT_CONF nCASC
N.C.
N.C.
nCS
N.C.
TDI
nCASC
GND
20-Pin PLCC
32-Pin TQFP
Functional Description
With SRAM-based devices, configuration data must be reloaded each time the system initializes, or when new configuration data is needed. Altera configuration devices store configuration data for SRAM-based APEX II, APEX 20K, Mercury, ACEX, and FLEX devices. Table 1 lists Altera configuration devices. Table 1. Configuration Devices Device
EPC16 EPC8 EPC4 EPC2 EPC1 (1) EPC1441 (1) EPC1213 (1) EPC1064 (1) EPC1064V Note to Table 1:
(1) These devices are one-time programable.
Description
16,000,000 x 1 bit with 3.3-V operation 8,000,000 x 1 bit with 3.3-V operation 4,000,000 x 1-bit device with 3.3-V operation 1,695,680 x 1-bit device with 5.0-V or 3.3-V operation 1,046,496 x 1-bit device with 5.0-V or 3.3-V operation 440,800 x 1-bit device with 5.0-V or 3.3-V operation 212,942 x 1-bit device with 5.0-V operation 65,536 x 1-bit device with 5.0-V operation 65,536 x 1-bit device with 3.3-V operation
Altera Corporation
nINIT_CONF
3
Configuration Devices for SRAM-based LUT Devices Data Sheet
Table 2 lists the configuration device used with each APEX II, APEX 20K, Mercury, ACEX 1K, and FLEX device. Table 2. Configuration Devices Used for Each APEX II, APEX 20K, Mercury, ACEX & FLEX Device (Part 1 of 2) Family
APEX II (1.5 V)
Device
EP2A15 EP2A25 EP2A40 EP2A70
Data Size EPC1064 EPC1213 EPC1441 EPC1 EPC2 EPC4 EPC8 EPC16 (Bits) EPC1064V
4,714,000 6,276,000 9,612,000 17,390,000 1,297,000 4,383,000 1,964,000 3,901,000 5,564,000 8,938,000 347,000 641,000 1,009,000 1,523,000 1,964,000 2,733,000 3,901,000 5,564,000 8,938,000 985,000 1,950,000 3,878,000 178,000 470,000 785,000 1,337,000 1 1 1 1 1 1 1 1 1 1 3 4 6 11 1 3 2 3 4 6 1 1 1 1 2 2 3 4 6 8 1 2 3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Mercury (1.8 V)
EP1M120 EP1M350
APEX 20KC EP20K200C (1.8 V) EP20K400C EP20K600C EP20K1000C APEX 20KE EP20K30E (1.8 V) EP20K60E EP20K100E EP20K160E EP20K200E EP20K300E EP20K400E EP20K600E EP20K1000E APEX 20K (2.5 V) EP20K100 EP20K200 EP20K400 ACEX 1K (2.5 V) EP1K10 EP1K30 EP1K50 EP1K100
EP20K1500E 12,011,000
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Altera Corporation
Configuration Devices for SRAM-Based LUT Devices Data Sheet
Table 2. Configuration Devices Used for Each APEX II, APEX 20K, Mercury, ACEX & FLEX Device (Part 2 of 2) Family Device Data Size EPC1064 EPC1213 EPC1441 EPC1 EPC2 EPC4 EPC8 EPC16 (Bits) EPC1064V
470,000 785,000 785,000 1,336,000 1,840,000 2,757,000 2,757,000 120,000 402,000 621,000 1,200,000 1,582,000 3,292,000 118,000 231,000 376,000 498,000 621,000 893,000 1,200,000 260,000 260,000 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
FLEX 10KE EPF10K30E (2.5 V) EPF10K50E EPF10K50S EPF10K100E EPF10K130E EPF10K200E EPF10K200S FLEX 10KA EPF10K10A (3.3 V) EPF10K30A EPF10K50V EPF10K100A EPF10K130V EPF10K250A FLEX 10K (5.0 V) EPF10K10 EPF10K20 EPF10K30 EPF10K40 EPF10K50 EPF10K70 EPF10K100 FLEX 6000/A (3.3 V) EPF6010A EPF6016 (5.0 V) / EPF6016A EPF6024A FLEX 8000A (5.0 V) EPF8282A / EPF8282AV (3.3 V) EPF8452A EPF8636A EPF8820A EPF81188A EPF1500A
EPF10K100B 1,2000,000
398,000 40,000 1 1
1 1
1 1
64,000 96,000 128,000 192,000 250,000
1
1 1 1 1
1 1 1 1 1
1 1 1 1 1
Altera Corporation
5
Configuration Devices for SRAM-based LUT Devices Data Sheet
Figure 3 shows the configuration device block diagram. Figure 3. Configuration Device Block Diagram
PLD (except FLEX 8000) Configuration Using an EPC2, EPC1, or EPC1441 (1)
DCLK Address Counter
Oscillator
CLK ENA nRESET
Oscillator Control nCS Error Detection Circuitry
Address
Decode Logic nCASC (2)
OE (3)
EPROM Array DATA Shift Register DATA
FLEX 8000 Device Configuration Using an EPC1, EPC1441, EPC1213, EPC1064, or EPC1064V
DCLK CLK ENA nRESET Address Counter
Address nCS OE EPROM Array DATA Shift Register
Decode Logic nCASC (2)
DATA
Notes to Figure 3:
(1) (2) (3) Do not use EPC2 devices to configure FLEX 6000 devices. The EPC1441, EPC1064, and EPC1064V devices do not support data cascading. The EPC2, EPC1, and EPC1213 devices support data cascading. The OE pin is a bidirectional open-drain pin.
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Altera Corporation
Configuration Devices for SRAM-Based LUT Devices Data Sheet
Device Configuration
The control signals for configuration devices--nCS, OE, and DCLK-- interface directly with APEX II, APEX 20K, Mercury, ACEX 1K, and FLEX device control signals. All APEX II, APEX 20K, Mercury, ACEX 1K, and FLEX devices can be configured by a configuration device without requiring an external intelligent controller. The configuration device's OE and nCS pins control the tri-state buffer on the DATA output pin, and enable the address counter (and the oscillator in EPC4, EPC 8, EPC16, EPC2, EPC1, and EPC1441 devices). When OE is driven low, the configuration device resets the address counter and tristates its DATA pin. The nCS pin controls the output of the configuration device. If nCS is held high after the OE reset pulse, the counter is disabled and the DATA output pin is tri-stated. When nCS is driven low, the counter and DATA output pin are enabled. When OE is driven low again, the address counter is reset and the DATA output pin is tri-stated, regardless of the state of nCS. 1 The EPC4, EPC8, EPC16, EPC2, EPC1, and EPC1441 devices determine the operation mode and whether the APEX 20K, Mercury, ACEX 1K, FLEX 10K, FLEX 8000, or FLEX 6000 protocols should be used when OE is driven high.
When the configuration device has driven out all of its data and has driven nCASC low, the device tri-states the DATA pin to avoid contention with other configuration devices. The EPC2 device allows the user to initiate configuration of the PLD via an additional pin, nINIT_CONF, that can be tied to the nCONFIG pin of the PLD(s) to be configured. A JTAG instruction causes the EPC4, EPC8, EPC16, and EPC2 device to drive nINIT_CONF low, which in turn pulls nCONFIG low. The EPC4, EPC8, EPC16, and EPC2 device then drives nINIT_CONF high to start configuration. When the JTAG state machine exits this state, nINIT_CONF releases nCONFIG and configuration is initiated. 1 An EPC4, EPC8, EPC16, and EPC2 device can be programmed with a POF generated for an EPC1 or EPC1441 device, however, an EPC2 device cannot configure FLEX 6000 or FLEX 8000 devices. An EPC1 device can be programmed using a POF generated for an EPC1441 device.
Altera Corporation
7
Configuration Devices for SRAM-based LUT Devices Data Sheet
APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K & FLEX 6000 Device Configuration
APEX 20K, Mercury, ACEX 1K, and FLEX devices can be configured with EPC4, EPC8, EPC16, EPC2, EPC1, or EPC1441 devices. FLEX 6000 devices can be configured with EPC1 or EPC1441 devices. APEX II devices can be configured with EPC2, EPC4, EPC8, and EPC16 devices. The EPC4, EPC8, EPC16, EPC2, EPC1, or EPC1441 device stores configuration data in its EPROM array and serially clocks data out with an internal oscillator. The OE, nCS, and DCLK pins supply the control signals for the address counter and the output tri-state buffer. The configuration device sends a serial bitstream of configuration data to its DATA pin, which is routed to the DATA0 or DATA input pin on the LUT-based PLD device. Figure 4 shows an LUT-based PLD configured with a single EPC2, EPC1, or EPC1441 device.
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Altera Corporation
Configuration Devices for SRAM-Based LUT Devices Data Sheet
Figure 4. ACEX 1K, APEX 20K, APEX II, FLEX 10K, FLEX 6000, or Mercury Device Configured with an EPC2, EPC1, or EPC1441 Configuration Device Note (1)
APEX II, ACEX 1K, Mercury, APEX 20KC, APEX 20K & FLEX 10K Devices VCC VCC VCC
LUT-Based PLD (3)
DCLK DATA0 nSTATUS CONF_DONE nCONFIG nCEO MSEL0 MSEL1 GND APEX 20KE Devices nCE
(2)
(2)
(2)
Configuration Device
DCLK DATA OE nCS nINIT_CONF (4)
(5)
GND VCC VCCINT (6) VCC
APEX 20KE PLD (7)
DCLK DATA0 nSTATUS CONF_DONE nCONFIG
(2)
(2)
(2)
Configuration Device
DCLK DATA OE nCS nINIT_CONF (4)
(8)
nCEO MSEL0 MSEL1 GND nCE GND
(5)
Notes to Figure 4:
(1) (2) Do not use EPC2 devices to configure FLEX 6000 devices. The pull-up resistor should be connected to the same supply voltage as the configuration device. All pull-up resistors are 1 k. APEX 20KE pull up resistors are 10 k. The OE, nCS, and nINIT_CONF pins on EPC2, EPC4, EPC8, and EPC16 devices have internal, user-configurable 1-k pull-up resistors. If internal pull-up resistors are used, external pull-up resistors should not be used on these pins. The Quartus II software uses the internal pull-up resistors by default. To turn off the internal pull-up resistors, check the Disable nCS and OE pull-ups on configuration device option when generating programming files. The diagram shows an APEX II, APEX 20K, Mercury, ACEX 1K, and FLEX device, which has MSEL0 and MSEL1 tied to ground. For FLEX 6000 devices, MSEL is tied to ground, and the DATA0 pin is named DATA. EPC4, EPC8, EPC16, and EPC2 configuration devices cannot be used with FLEX 6000 devices. All other connections are the same for APEX II, APEX 20K, Mercury, ACEX 1K, and FLEX devices. The nINIT_CONF pin is only available on EPC2, EPC4, EPC8, and EPC16 devices and has an internal pull up of 1 k that is always active. If nINIT_CONF is not available or not used, nCONFIG must be pulled to VCC either directly or through a 1-k resistor. The nCEO pin is left unconnected. To ensure successful configuration between APEX 20KE and configuration devices in all possible power-up sequences, pull up nCONFIG to VCCINT. This diagram is for APEX 20KE devices only. To isolate the 1.8-V and 3.3-V power supplies when configuration APEX 20KE devices, add a diode between the APEX 20KE device's nCONFIG pin and the configuration device's nINIT_CONF pin. Select a diode with a threshold voltage (VT) less than or equal to 0.7 V. The diode will make the nINIT_CONF pin an open-drain pin; the pin will only be able to drive low or tri-state.
(3)
(4)
(5) (6) (7) (8)
Altera Corporation
9
Configuration Devices for SRAM-based LUT Devices Data Sheet
Table 3 describes EPC2, EPC1, and EPC1441 pin functions during APEX II, APEX 20K, Mercury, ACEX 1K, and FLEX device configuration. For information on EPC4, EPC8, and EPC16 devices, refer to Enhanced Configuration Devices (EPC4, EPC8, & EPC16) Data Sheet. Table 3. EPC2, EPC1, & EPC1441 Pin Functions During APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K & FLEX 6000 Configuration (Part 1 of 3) Notes (1), (2) Pin Name Pin Number 8-Pin PDIP (3)
DATA 1
20-Pin 32-Pin PLCC TQFP (4)
2 31
Pin Type
Description
Output
Serial data output. The DATA pin is tri-stated before configuration when the nCS pin is high, and after the configuration device finishes sending its configuration data. This operation is independent of the device's position in the cascade chain. DCLK is a clock output when configuring with a single configuration device or when the configuration device is the first device in a configuration device chain. DCLK is a clock input for subsequent configuration devices in a configuration device chain. Rising edges on DCLK increment the internal address counter and present the next bit of data to the DATA pin. The counter is incremented only if the OE input is held high, the nCS input is held low, and all configuration data has not been transferred to the target device. When configuring with the first EPC2 or EPC1 device in a configuration device chain or with a single EPC1441 device, the DCLK pin drives low after configuration is complete or when OE is low. Output enable (active high) and reset (active low). A low logic level resets the address counter. A high logic level enables DATA and permits the address counter to count. If this pin is low (reset) during configuration, the internal oscillator becomes inactive and DCLK drives low. See "Error Detection Circuitry" on page 23. Chip select input (active low). A low input allows DCLK to increment the address counter and enables DATA to drive out. If the EPC1 or EPC2 is reset with nCS low, the device initializes as the first device in a configuration chain. If the EPC1 or EPC2 device is reset with nCS high, the device initializes as the subsequent device in the chain.
DCLK
2
4
2
I/O
OE (5)
3
8
7
OpenDrain I/O
nCS (5)
4
9
10
Input
10
Altera Corporation
Configuration Devices for SRAM-Based LUT Devices Data Sheet
Table 3. EPC2, EPC1, & EPC1441 Pin Functions During APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K & FLEX 6000 Configuration (Part 2 of 3) Notes (1), (2) Pin Name Pin Number 8-Pin PDIP (3)
nCASC (6) 6
20-Pin 32-Pin PLCC TQFP (4)
12 15
Pin Type
Description
Output
Cascade select output (active low). This output goes low when the address counter has reached its maximum value. In a chain of EPC1 or EPC2 devices, the nCASC pin of one device is connected to the nCS pin of the next device, which permits DCLK to clock data from the next EPC1 or EPC2 device in the chain. Allows the INIT_CONF JTAG instruction to initiate configuration. This pin is connected to the nCONFIG pin of the LUT device to initiate configuration from the EPC2 via a JTAG instruction. If multiple EPC2 devices are used to configure an ACEX, APEX, FLEX or Mercury device, only the first EPC2 has its nINIT_CONF pin tied to the device's nCONFIG pin. JTAG data input pin. Connect this pin to VCC if the JTAG circuitry is not used. JTAG data output pin. Do not connect this pin if the JTAG circuitry is not used. JTAG mode select pin. Connect this pin to VCC if the JTAG circuitry is not used. JTAG clock pin. Connect this pin to ground if the JTAG circuitry is not used. Mode select for VCC supply. VCCSEL must be connected to ground if the device uses a 5.0-V power supply (i.e., VCC = 5.0 V). VCCSEL must be connected to VCC if the device uses a 3.3-V power supply (i.e., VCC = 3.3 V). Mode select for VPP. VPPSEL must be connected to ground if VPP uses a 5.0-V power supply (i.e., VPP = 5.0 V). VPPSEL must be connected to VCC if VPP uses a 3.3-V power supply (i.e, VPP = 3.3 V). Programming power pin. For the EPC2 device, this pin is normally tied to VCC. If the EPC2 VCC is 3.3 V, VPP can be tied to 5.0 V to improve in-system programming times. For EPC1 and EPC1441 devices, VPP must be tied to VCC.
nINIT_CONF - (5), (7)
13
16
OpenDrain Output
TDI (7) TDO (7) TMS (7) TCK (7) VCCSEL (7)
- - - - -
11 1 19 3 5
13 28 25 32 3
Input Output Input Input Input
VPPSEL (7)
-
14
17
Input
VPP (7)
-
18
23
Power
Altera Corporation
11
Configuration Devices for SRAM-based LUT Devices Data Sheet
Table 3. EPC2, EPC1, & EPC1441 Pin Functions During APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K & FLEX 6000 Configuration (Part 3 of 3) Notes (1), (2) Pin Name Pin Number 8-Pin PDIP (3)
VCC GND 7, 8 5
20-Pin 32-Pin PLCC TQFP (4)
20 10 27 12
Pin Type
Description
Power
Power pin.
Ground Ground pin. A 0.2-F decoupling capacitor must be placed between the VCC and GND pins.
Notes to Table 3:
(1) (2) (3) (4) (5) (6) (7) Do not use EPC2 devices to configure FLEX 6000 devices. Pin-out information for EPC8 and EPC16 configuration devices, please refer to each respective data sheet. This package is available for EPC1 and EPC1441 devices only. This package is available for EPC2 and EPC1441 devices only. The OE, nCS, and nINIT_CONF pins on EPC2 devices have internal, user-configurable 1-k pull-up resistors. If internal pull-up resistors are used, external pull-up resistors should not be used on these pins. The EPC1441 device does not support data cascading. EPC2 and EPC1 devices support data cascading. This pin applies to the EPC2 device only.
APEX II, APEX 20K, Merucry, ACEX 1K, FLEX 10K & FLEX 6000 Device Configuration with Multiple EPC2 or EPC1 Configuration Devices
When configuration data for APEX II, APEX 20K, Mercury, ACEX 1K, and FLEX devices exceeds the capacity of a single EPC2 or EPC1 configuration device, multiple EPC2 or EPC1 devices can be cascaded together. If multiple EPC2 or EPC1 devices are required, the nCASC and nCS pins provide handshaking between the devices. 1 EPC8 and EPC16 configuration devices cannot be cascaded together. The EPC1441 device does not support data cascading.
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Altera Corporation
Configuration Devices for SRAM-Based LUT Devices Data Sheet
When configuring APEX II, APEX 20K, Mercury, ACEX 1K, and FLEX 10K devices with cascaded EPC2 or EPC1 devices, the position of the EPC2 or EPC1 device in the chain determines its operation. Similarly, when configuring FLEX 6000 devices with cascaded EPC1 devices, the position of the EPC1 device in the chain determines its operation. When the first or master device in a configuration device chain is powered-up or reset and the nCS pin is driven low, the master device controls configuration. The master device supplies all clock pulses to one or more LUT-based PLDs and to any subsequent slave devices during configuration. The master EPC2 or EPC1 device also provides the first stream of data to the LUT-based PLD during multi-device configuration. After the master EPC2 or EPC1 device finishes sending configuration data, the master EPC2 or EPC1 device drives its nCASC pin low, which drives the nCS pin of the first slave EPC2 or EPC1 device low. This action causes the slave EPC2 or EPC1 device to send configuration data to the LUT-based PLDs. The master EPC2 or EPC1 device clocks all subsequent slave devices until configuration is complete. Once all configuration data is transferred and the nCS pin on the master EPC2 or EPC1 device is driven high by the LUTbased PLD's CONF_DONE pin, the master EPC2 or EPC1 device clocks 16 additional cycles to initialize the LUT-based PLD(s). The master EPC2 or EPC1 device then goes into zero-power (idle) state. If nCS on the master EPC2 or EPC1 device is driven high before all configuration data is transferred, or if nCS is not driven high after all configuration data is transferred, the master EPC2 or EPC1 device drives the APEX 20K, Mercury, ACEX 1K, and FLEX device's nSTATUS pin low, indicating a configuration error. Configuration automatically restarts if the project is compiled with the Auto-Restart Configuration on Frame Error option turned on in the MAX+PLUS II software's Global Project Device Options dialog box (Assign menu). Figure 5 shows an APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K, or FLEX 6000 device configured with two EPC2 or EPC1 devices. Additional EPC2 or EPC1 devices can be added by connecting nCASC to nCS of the subsequent slave EPC2 or EPC1 device in the chain and connecting DCLK, DATA, and OE in parallel. 1 A mixture of APEX 20K, Mercury, ACEX 1K, FLEX 10K, and FLEX 6000 devices can be configured in the same chain. A mixture of FLEX 10K, FLEX 10KA, FLEX 10KE, and 5.0-V and 3.3-V FLEX 6000 devices can be configured in the same chain. See "Configuration Chain with Multiple Voltage Levels" on page 25.
Altera Corporation
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Configuration Devices for SRAM-based LUT Devices Data Sheet
Figure 5. APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K, or FLEX 6000 Device Configured with Two EPC2 or EPC1 Configuration Devices Note (1)
APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K, or FLEX 6000 Devices
VCC VCC
(2, 3) LUT-Based PLD (4)
DCLK DATA0 nSTATUS CONF_DONE nCONFIG MSEL0 MSEL1
(2, 3)
Configuration Device 1
DCLK DATA OE nCS nCASC (5) nINIT_CONF (6)
Configuration Device 2
DCLK DATA nCS OE
nCE
GND
GND
(7) APEX 20KE Devices
VCC VCCINT VCC
APEX 20KE Device
DCLK DATA0 nSTATUS CONF_DONE nCONFIG nCEO MSEL0 MSEL1 GND nCE
(2)
(2)
(2)
Configuration Device
DCLK DATA OE nCS nINIT_CONF (6)
N.C. (9)
(8)
GND
Notes to Figure 5:
(1) (2) (3) Do not use EPC2 devices to configure FLEX 6000 devices. The pull-up resistor should be connected to the same supply voltage as the configuration device. All pull-up resistors are 1 k (APEX 20KE pull-resistors are 10 k). The OE and nCS pins on EPC2 devices have internal, user-configurable 1-k pull-up resistors. If internal pull-up resistors are used, external pull-up resistors should not be used on these pins. The diagram shows an APEX II, APEX 20K, Mercury, ACEX 1K, and FLEX device, which has MSEL0 and MSEL1 tied to ground. For FLEX 6000 devices, MSEL is tied to ground, and the DATA0 pin is named DATA. EPC8, EPC16, and EPC2 devices cannot be used with FLEX 6000 devices. All other connections are the same for FLEX 6000 devices. The Quartus II software uses the internal pull-up resistors by default. To turn off the internal pull-up resistors, check the Disable nCS and OE pull-ups on configuration device option when generating programming files. EPC4, EPC8, and EPC16 devices cannot be cascaded. The nINIT_CONF pin is only available on EPC2 devices and has an internal pull up of 1 k that is always active. If nINIT_CONF is not available or not used, nCONFIG must be pulled to V CC either directly or through a 1-k resistor. To ensure successful configuration between APEX 20KE and configuration devices in all possible power-up sequences, pull up nCONFIG to V CCINT. To isolate the 1.8-V and 3.3-V power supplies when configuring APEX 20KE devices, add a diode between the APEX 20KE device's nCONFIG pin and the configuration device's nINIT_CONF pin. Select a diode with a threshold voltage (V T ) less than or equal to 0.7 V. The diode will make the nINIT_CONF pin an open-drain pin; the pin will only be able to drive low or tri-state. The nCEO pin is left unconnected.
(4)
(5) (6) (7) (8)
(9)
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Altera Corporation
Configuration Devices for SRAM-Based LUT Devices Data Sheet
Figure 6 shows two APEX II, APEX 20K, Mercury, ACEX 1K, and FLEX devices configured with two EPC2 or EPC1 devices. Figure 6. Two ACEX 1K, APEX 20K, APEX II, FLEX 10K, FLEX 6000, or Mercury Devices Configured with Two EPC2 or EPC1 Configuration Devices Note (1)
VCC APEX II, ACEX 1K, Mercury, APEX 20KC, APEX 20K, FLEX 10K, & FLEX 6000 Devices VCC VCC
(2)
(2)
(2)
LUT-Based PLD (3) MSEL0 MSEL1 DCLK DATA0 nSTATUS CONF_DONE nCONFIG GND nCE
LUT-Based PLD (3) MSEL0 MSEL1 DCLK DATA0 nSTATUS CONF_DONE nCONFIG
Configuration Device 1 DCLK DATA OE nCS nCASC (4) nINIT_CONF (5)
Configuration Device 2 DCLK DATA nCS OE
GND
nCEO
nCE
GND
APEX 20KE Devices
VCC
VCC VCCINT (6)
(2)
(2)
(2)
APEX 20KE PLD (7) MSEL0 MSEL1 DCLK DATA0 nSTATUS CONF_DONE nCONFIG GND nCE
APEX 20KE PLD (7) MSEL0 MSEL1 DCLK DATA0 nSTATUS CONF_DONE nCONFIG
Configuration Device 1 DCLK DATA OE nCS nCASC (4) nINIT_CONF (5)
Configuration Device 2 DCLK DATA nCS OE
GND
(8)
nCEO nCE
GND
Altera Corporation
15
Configuration Devices for SRAM-based LUT Devices Data Sheet Notes to Figure 6:
(1) (2) Do not use EPC2 devices to configure FLEX 6000 devices. The pull-up resistor should be connected to the same supply voltage as the configuration device. All pull-up resistors are 1 k (APEX 20KE pull-resistors are 10 k). The OE and nCS pins on EPC2 devices have internal, userconfigurable 1-k pull-up resistors. If internal pull-up resistors are used, external pull-up resistors should not be used on these pins. The Quartus II software uses the internal pull-up resistors by default. To turn off the internal pull-up resistors, check the Disable nCS and OE pull-ups on configuration device option when generating programming files. The diagram shows an APEX II, APEX 20K, Mercury, ACEX 1K, or FLEX 10K device, which has MSEL0 and MSEL1 tied to ground. For FLEX 6000 devices, MSEL is tied to ground, and the DATA0 pin is named DATA. EPC2 cannot be used with FLEX 6000 devices. All other connections are the same for FLEX 6000 devices. EPC4, EPC8, and EPC16 devices cannot be cascaded. The nINIT_CONF pin is only available on EPC2 devices and has an internal pull up of 1 k that is always active. If nINIT_CONF is not available or not used, nCONFIG must be pulled to V CC either directly or through a 1-k resistor. To ensure successful configuration between APEX 20KE and configuration devices in all possible power-up sequences, pull up nCONFIG to V CCINT. This diagram is for APEX 20KE devices only. To isolate the 1.8-V and 3.3-V power supplies when configuration APEX 20KE devices, add a diode between the APEX 20KE device's nCONFIG pin and the configuration device's nINIT_CONF pin. Select a diode with a threshold voltage (V T) less than or queal to 0.7 V. The diode will make the nINIT_CONF pin an open-drain pin; the pin will only be able to drive low or tri-state.
(3)
(4) (5) (6) (7) (8)
f
For more information on APEX 20K, ACEX 1K, FLEX 10K, or FLEX 6000 device configuration, see Application Note 116 (Configuring ACEX 1K, APEX 20K, FLEX 10K & FLEX 6000 Devices). Figure 7 shows the timing waveform for the configuration device scheme.
Figure 7. Configuration Device Scheme Timing Waveform
nINIT_CONF or VCC/nCONFIG OE/nSTATUS nCS/CONF_DONE tDSU DCLK DATA User I/O INIT_DONE tOEZX D0 tCO D1 tCL tDH D2 D3 Dn tPOR
tCH
(1) User Mode
Tri-State
Tri-State
(2)
Notes to Figure 7:
(1) (2) The configuration devivce will drive DATA low after configuration. APEX II and APEX 20K devices (except EP2A70 devices) enter user mode 40 clock cycles after CONF_DONE goes high. EP2A70 devices enter user mode 72 clock cycles after CONF_DONE goes high. FLEX 10K and FLEX 6000 devices enter user mode 10 clock cycles after CONF_DONE goes high. Mercury devices enter user mode 136 clock cycles after CONF_DONE goes high.
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Altera Corporation
Configuration Devices for SRAM-Based LUT Devices Data Sheet
Table 4 defines the APEX 20K, FLEX 10K, and FLEX 6000 timing parameters when using EPC2 devices at 3.3 V. Table 4. APEX 20K, FLEX 10K & FLEX 6000 Timing Parameters using EPC2 Devices at 3.3 V Note (1) Symbol
tPOR tOEZX tCH tCL tDSU tDH tCO tOEW fCLK
(1) (2)
Parameter
POR delay (2) OE high to DATA output enabled DCLK high time DCLK low time Data setup time before rising edge on DCLK Data hold time after rising edge on DCLK DCLK to DATA out OE low pulse width to guarantee counter reset DCLK frequency
Min
Max
200 80
Units
ms ns ns ns ns ns
40 40 30 0
100 100
30 100 5 12.5
ns ns MHz
Notes to Table 4:
For more information regarding EPC4, EPC8, or EPC16 configuration device timing parameters, see the Enhanced Configuration Device (EPC4, EPC8 & EPC16) Data Sheet. The configuration device imposes a POR delay upon initial power-up to allow the voltage supply to stabilize. Subsequent reconfigurations do not incur this delay.
Altera Corporation
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Configuration Devices for SRAM-based LUT Devices Data Sheet
Table 5 defines the APEX 20K, FLEX 10K, and FLEX 6000 timing parameters when using EPC1 and EPC1441 devices at 3.3 V. Table 5. APEX 20K, FLEX 10K & FLEX 6000 Timing Parameters using EPC1 & EPC1441 Devices at 3.3 V Note (1) Symbol
tPOR tOEZX tCH tCL tDSU tDH tCO tOEW fCLK
(1) (2)
Parameter
POR delay (2) OE high to DATA output enabled DCLK high time DCLK low time Data setup time before rising edge on DCLK Data hold time after rising edge on DCLK DCLK to DATA out OE low pulse width to guarantee counter reset DCLK frequency
Min
Max
200 80
Units
ms ns ns ns ns ns
50 50 30 0
250 250
30 100 2 10
ns ns MHz
Notes to Table 5:
For more information regarding EPC4, EPC8, or EPC16 configuration device timing parameters, see the Enhanced Configuration Device (EPC4, EPC8 & EPC16) Data Sheet. The configuration device imposes a POR delay upon initial power-up to allow the voltage supply to stabilize. Subsequent reconfigurations do not incur this delay.
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Altera Corporation
Configuration Devices for SRAM-Based LUT Devices Data Sheet
Table 6 defines the APEX 20K, FLEX 10K, and FLEX 6000 timing parameters when using EPC2, EPC1, and EPC1441 devices at 5.0 V. Table 6. APEX 20K, FLEX 10K & FLEX 6000 Timing Parameters using EPC2, EPC1 & EPC1441 Devices at 5.0 V Notes (1), (2) Symbol
tPOR tOEZX tCH tCL tDSU tDH tCO tOEW fCLK
(1) (2) (3)
Parameter
POR delay (3) OE high to DATA output enabled DCLK high time DCLK low time Data setup time before rising edge on DCLK Data hold time after rising edge on DCLK DCLK to DATA out OE low pulse width to guarantee counter reset DCLK frequency
Min
Max
200 50
Units
ms ns ns ns ns ns
30 30 30 0
75 75
30 100 6.7 16.7
ns ns MHz
Notes to Table 6:
Do not use EPC16, EPC8, EPC4, or EPC2 devices to configure FLEX 6000 devices. For more information regarding EPC4, EPC8, or EPC16 configuration device timing parameters, see the Enhanced Configuration Device (EPC4, EPC8 & EPC16) Data Sheet. The configuration device imposes a POR delay upon initial power-up to allow the voltage supply to stabilize. Subsequent reconfigurations do not incur this delay.
FLEX 8000 Device Configuration
FLEX 8000 devices differ from ACEX 1K, APEX 20K, APEX II, FLEX 10K, and FLEX 6000 devices in that they have internal oscillators that can provide a DCLK signal to the configuration device. The configuration device sends configuration data out as a serial bitstream on the DATA output pin. This data is routed into the FLEX 8000 device via the DATA0 input pin. The EPC1, EPC1441, EPC1213, EPC1064, and EPC1064V configuration devices support this type of configuration.
Altera Corporation
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Configuration Devices for SRAM-based LUT Devices Data Sheet
EPC1 and EPC1441 devices can replace the EPC1213, EPC1064, and EPC1064V configuration devices. The EPC1 or EPC1441 device automatically emulates the EPC1213, EPC1064, or EPC1064V when it is programmed with the appropriate POF. When the EPC1 or EPC1441 device is programmed with an EPC1213, EPC1064, or EPC1064V POF, the FLEX 8000 device drives the EPC1 or EPC1441 device's OE pin high and clocks the EPC1 or EPC1441 device. One EPC1 device can store more configuration data than the EPC1064, EPC1064V, EPC1213, or EPC1441 device. Therefore, designers can use one type of configuration device for all FLEX devices. In addition, a single EPC1 or EPC1441 device can configure any FLEX 8000 device. For multi-device configuration of FLEX 8000 devices, the nCASC and nCS pins provide handshaking between multiple configuration devices, allowing several cascaded EPC1 or EPC1213 devices to serially configure multiple FLEX 8000 devices. The EPC1441, EPC1064, and EPC1064V do not support data cascading. Figure 8 shows a FLEX 8000 device configured with a single EPC1, EPC1441, EPC1213, EPC1064, or EPC1064V configuration device. Figure 8. FLEX 8000 Device Configured with an EPC1, EPC1441, EPC1213, EPC1064, or EPC1064V Configuration Device
VCC (1) VCC (1) VCC (1)
(2)
(2)
FLEX 8000 Device "0" "0" "0"
nS/P MSEL1 MSEL0 CONF_DONE nSTATUS DCLK
Configuration Device
nCS OE DCLK DATA
DATA0 nCONFIG
Notes to Figure 8:
(1) (2) The pull-up resistor should be connected to the same supply voltage as the configuration device. All pull-up resistors are 1 k.
Figure 9 shows three FLEX 8000 devices configured with two EPC1 or EPC1213 configuration devices.
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Altera Corporation
Configuration Devices for SRAM-Based LUT Devices Data Sheet
Figure 9. FLEX 8000 Multi-Device Configuration with Two EPC1 or EPC1213 Configuration Devices
VCC (1) VCC (1) VCC
(1)
(2)
VCC
(2) (1)
VCC
(1)
FLEX 8000 Device 1 "0" "0" "0"
nS/P MSEL1 MSEL0 CONF_DONE nSTATUS DCLK
(2)
(2)
Configuration Device 1
nCASC DATA nCS OE DCLK
Configuration Device 2
DATA nCS OE DCLK
DATA0 nCONFIG
VCC
(1)
(2)
FLEX 8000 Device 2 "0" "1" "0"
nS/P MSEL1 MSEL0 CONF_DONE nSTATUS
DCLK DATA0 nCONFIG
VCC
(1)
(2)
FLEX 8000 Device 3 "0" "1" "0"
nS/P MSEL1 MSEL0 CONF_DONE nSTATUS
DCLK DATA0 nCONFIG
Notes to Figure 9:
(1) (2) The pull-resistor should be connected to the same supply voltage as the confiuration device. All pull-up resistors are 1 k.
Altera Corporation
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Configuration Devices for SRAM-based LUT Devices Data Sheet
Table 7 describes the pin functions of all configuration devices during FLEX 8000 device configuration. Table 7. Configuration Device Pin Functions During FLEX 8000 Device Configuration Pin Name 8-Pin PDIP (1)
DATA 1
Pin Number 20-Pin PLCC
2
32-Pin TQFP (2)
31
Pin Type
Description
Output Serial data output. The DATA pin is tri-stated before configuration when the nCS pin is high and after the configuration device finishes sending its configuration data. This operation is independent of the device's position in the cascade chain. Input DCLK is a clock input when using EPC1, EPC1213, EPC1064, and EPC1064V configuration devices. Rising edges on DCLK increment the internal address counter and present the next bit of data to the DATA pin. The counter is incremented only if the OE input is held high, the nCS input is held low, and all configuration data has not been transferred to the target device. Output enable (active high) and reset (active low). A low logic level resets the address counter. A high logic level enables DATA and permits the address counter to count. Chip-select input (active low). A low input allows DCLK to increment the address counter and enables DATA. Cascade-select output (active low). This output goes low when the address counter has reached its maximum value. The nCASC output is usually connected to the nCS input of the next device in a configuration chain, so the next DCLK clocks data out of the next device. Power pin.
DCLK
2
4
2
OE
3
8
7
OpenDrain I/O Input Output
nCS (3) nCASC
4 6
9 12
10 15
VCC GND
7, 8 5
20 10
27 12
Power
Ground Ground pin. A 0.2-F decoupling capacitor must be placed between the VCC and GND pins.
Notes: to Table 7
(1) (2) (3) This package is available for EPC1, EPC1441, EPC1213, EPC1064, and EPC1064V devices only. This package is available for EPC1441, EPC1064, and EPC1064V devices only. The EPC1441, EPC1064, and EPC1064V devices do not support data cascading. The EPC1 and EPC1213 devices support data cascading for FLEX 8000 devices.
f
For more information on FLEX 8000 device configuration, see the following documents:

Application Note 33 (Configuring FLEX 8000 Devices) Application Note 38 (Configuring Multiple FLEX 8000 Devices)
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Altera Corporation
Configuration Devices for SRAM-Based LUT Devices Data Sheet
Power & Operation
This section describes Power-On Reset (POR) delay, error detection, and 3.3-V and 5.0-V operation of Altera configuration devices.
Power-On Reset
During initial power-up, a POR delay occurs to permit voltage levels to stabilize. When configuring an APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K, or FLEX 6000 device with an EPC4, EPC8, EPC16, EPC2, EPC1, or EPC1441 device, the POR delay occurs inside the configuration device, and the POR delay is a maximum of 200 ms. When configuring a FLEX 8000 device with an EPC1213, EPC1064, or EPC1064V device, the POR delay occurs inside the FLEX 8000 device, and the POR delay is typically 100 ms, with a maximum of 200 ms.
Error Detection Circuitry
The EPC4, EPC8, EPC16, EPC2, EPC1, and EPC1441 configuration devices have built-in error detection circuitry for configuring APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K, or FLEX 6000 devices only. Built-in error-detection circuitry uses the nCS pin of the configuration device, which monitors the CONF_DONE pin on the APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K, or FLEX 6000 device. An error condition occurs if the CONF_DONE pin does not go high after all the configuration data has been sent, or if the CONF_DONE pin goes high before the configuration device has completed sending configuration data. When an error condition occurs, the configuration device drives its OE pin low, which drives the APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K, or FLEX 6000 device's nSTATUS pin low, indicating an error. After an error, configuration automatically restarts if the Auto-Restart Configuration on Frame Error option is turned on in the Global Project Device Options dialog box (Assign menu) in the MAX+PLUS II software. For APEX 20K, APEX II, and Mercury devices, the Quartus II software provides a similar option. In addition, if the APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K, or FLEX 6000 device detects a cyclic redundancy code (CRC) error in the received data, it may also flag the error by driving nSTATUS low. This low signal on nSTATUS resets the configuration device, allowing reconfiguration. CRC checking is performed when configuring all APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K, or FLEX 6000 devices.
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Configuration Devices for SRAM-based LUT Devices Data Sheet
3.3-V or 5.0-V Operation
EPC2, EPC1, and EPC1441 devices can configure 5.0-V, 3.3-V, or 2.5-V devices. For each configuration device, an option must be set for 5.0-V or 3.3-V operation (EPC4, EPC8, and EPC16 devices are 3.3 V). For EPC1 and EPC1441 configuration devices, the Use Low-Voltage Configuration EPROM option in the Global Project Device Options dialog box (Assign menu) in the MAX+PLUS II software sets this parameter. (For APEX 20K, APEX II, and Mercury devices, the Quartus II software provides a similar option.) For EPC2 devices, this option is set externally by the VCCSEL pin. In addition, the EPC2 device has an externally controlled option, set by the VPPSEL pin, to adjust the programming voltage to 5.0 V or 3.3 V. The functions of the VCCSEL and VPPSEL pins are described below.
VCCSEL pin--For EPC2 configuration devices, 5.0-V or 3.3-V operation is controlled by the VCCSEL option pin. The device functions in 5.0-V mode when VCCSEL is connected to GND; the device functions in 3.3-V mode when VCCSEL is connected to VCC. VPPSEL pin--The EPC2 VPP programming power pin is normally tied to VCC . For EPC2 devices operating with a 3.3-V supply, it is possible to improve EPC2 in-system programming times by providing VPP with a 5.0-V supply. For all other devices, VPP must be tied to VCC. The EPC2 device's VPPSEL pin must be set in accordance with the EPC2 VPP pin. If the VPP pin is supplied by a 5.0-V supply, VPPSEL must be connected to GND; if the VPP pin is supplied by a 3.3-V power supply, VPPSEL must be connected to VCC.
Table 8 describes the relationship between the VCC and VPP voltage levels and the required logic level for VCCSEL and VPPSEL (i.e., high or low logic level). Table 8. VCCSEL & VPPSEL Pin Functions on the EPC2 VCC Voltage Level VPP Voltage Level VCCSEL Pin Logic VPPSEL Pin Logic (V) (V) Level Level
3.3 3.3 5.0 3.3 5.0 5.0 High High Low High Low Low
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Altera Corporation
Configuration Devices for SRAM-Based LUT Devices Data Sheet
For EPC1 and EPC1441 configuration devices, 3.3-V or 5.0-V operation is controlled by a programming bit in the POF. The programming bit value is determined by the core supply voltage of the targeted device during design compilation with the MAX+PLUS II software. For example, EPC1 devices are programmed automatically to operate in 3.3-V mode when configuring FLEX 10KA devices, which have a VCC voltage of 3.3 V. In this example, the EPC1 device's VCC pin is connected to a 3.3-V power supply. Designers may choose to set the configuration device for low voltage when using the MultiVoltTM feature, which allows an ACEX, APEX, APEX II, FLEX, or Mercury device to bridge between systems operating with different voltages. When compiling for 3.3-V FLEX 6000 devices, set the configuration device for low-voltage operation. To set the EPC1 and EPC1441 configuration devices for low-voltage operation, turn on the Low-Voltage I/O option in the Global Project Device Options dialog box (Assign menu) in the MAX+PLUS II software.
Configuration Chain with Multiple Voltage Levels
An EPC2 or EPC1 device can configure a device chain with multiple voltage levels. All 3.3-V and 2.5-V ACEX, APEX, APEX II, FLEX, and Mercury devices can be driven by higher-voltage signals. When configuring a mixed-voltage device chain, the APEX II, APEX 20K, Mercury, ACEX 1K, or FLEX devices' VCCINT and VCCIO pins may be connected to 2.5 V, 3.3 V, or 5.0 V, depending upon the device. The configuration device may be powered at 3.3 V or 5.0 V. If an EPC1, EPC1441, EPC1213, EPC1064, or EPC1064V configuration device is powered at 3.3 V, the nSTATUS and CONF_DONE pull-up resistors must be connected to 3.3 V. If these configuration devices are powered at 5.0 V, the nSTATUS and CONF_DONE pull-up resistors must be connected to 3.3 V or 5.0 V.
Altera Corporation
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Configuration Devices for SRAM-based LUT Devices Data Sheet
At 3.3-V operation, all EPC2 inputs are 5.0-V tolerant, except DATA, DCLK, and nCASC. The DATA, DCLK, and nCEO pins are used only to interface between the EPC2 configuration device and the APEX II, APEX 20K, Mercury, ACEX 1K, or FLEX 10K device it is configuring. The voltage tolerances of all EPC2 pins at 5.0 V and 3.3 V are listed in Table 9. Table 9. EPC2 Input & Bidirectional Pin Voltage Tolerance Pin 5.0-V Operation 5.0-V Tolerant
DATA DCLK nCASC OE nCS VCCSEL VPPSEL nINIT_CONF TDI TMS TCK
3.3-V Operation 5.0-V Tolerant 3.3-V Tolerant v v v v v v v v v v v v v v v v v v v
3.3-V Tolerant v v v v v v v v v v v
v v v v v v v v v v v
f
For more information on APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K, or FLEX 6000 devices, see the following documents:

ACEX 1K Programmable Logic Device Family Data Sheet APEX 20K Programmable Logic Device Family Data Sheet APEX II Programmable Logic Device Family Data Sheet FLEX 10K Embedded Programmable Logic Family Data Sheet FLEX 10KE Embedded Programmable Logic Family Data Sheet FLEX 8000 Programmable Logic Device Family Data Sheet FLEX 6000 Programmable Logic Device Family Data Sheet Mercury Programmable Logic Device Family Data Sheet
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Altera Corporation
Configuration Devices for SRAM-Based LUT Devices Data Sheet
Programming & Configuration File Support
The Quartus II and MAX+PLUS II development systems provide programming support for Altera configuration devices. The Quartus II and MAX+PLUS II software automatically generates a POF to program each configuration device in a project. In a multi-device project, the software can combine the programming files for multiple ACEX, APEX, APEX II, FLEX, or Mercury devices into one or more configuration devices. The software allows you to select the appropriate configuration device to most efficiently store the data for each APEX II, APEX 20K, Mercury, ACEX 1K, or FLEX device. Moreover, when compiling for ACEX 1K, FLEX 10KA, FLEX 10KE, or Mercury devices, the MAX+PLUS II software automatically defaults to generate the EPC1 or EPC1441 POF with the programming bit set for 3.3-V operation. All Altera configuration devices are programmable using Altera programming hardware in conjunction with the Quartus II or MAX+PLUS II software. In addition, many manufacturers offer programming hardware that supports other Altera configuration devices. EPC4, EPC8, EPC16, and EPC2 configuration devices can be programmed in-system through its industry-standard 4-pin JTAG interface. ISP capability in the EPC2, EPC4, EPC8, and EPC16 devices provides ease in prototyping and updating APEX II, APEX 20K, Mercury, ACEX 1K, or FLEX device functionality. The EPC8 and EPC16 devices can be programmed in-system via test equipment using SVF Files, Jam STAPL Files (.jam), or Jam STAPL Byte-Code Files (.jbc), embedded processors using the Jam programming and test language, and the MAX+PLUS II or Quartus II software via the MasterBlaster or ByteBlasterMV download cables. When programming multiple EPC2 devices in a JTAG chain, the Quartus II and MAX+PLUS II software and other programming methods employ concurrent programming to simultaneously program multiple devices and reduce programming time. EPC2, EPC4, EPC8, and EPC16 devices can be programmed and erased up to 100 times. After programming an EPC2, EPC4, EPC8, or EPC16 device in-system, APEX II, APEX 20K, Mercury, ACEX 1K, or FLEX device configuration can be initiated by including the EPC2 JTAG configuration instruction. See Table 10 on page 28.
f
For more information on programming and configuration support, see the following documents:

Altera Programming Hardware Data Sheet Programming Hardware Manufacturers MasterBlaster Serial/USB Communications Cable Data Sheet ByteBlasterMV Parallel Port Download Cable Data Sheet ByteBlaster Parallel Port Download Cable Data Sheet BitBlaster Serial Download Cable Data Sheet
Altera Corporation
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Configuration Devices for SRAM-based LUT Devices Data Sheet
IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing f
The EPC2 provides JTAG BST circuitry that complies with the IEEE Std. 1149.1-1990 specification. JTAG boundary-scan testing can be performed before or after configuration, but not during configuration. The EPC2 device supports the JTAG instructions shown in Table 10. The ISP circuitry in EPC2, EPC4, EPC8, and EPC16 devices is compatible with tools that support the IEEE Std. 1532. The IEEE Std. 1532 is a standard developed to allow concurrent ISP between multiple PLD vendors. For EPC4, EPC8, and EPC16 JTAG instruction, refer to the Enhanced Configuration Devices (EPC4, EPC8, & EPC16) Data Sheet.
Table 10. EPC2 JTAG Instructions JTAG Instruction
SAMPLE/PRELOAD EXTEST BYPASS
Description
Allows a snapshot of a signal at the device pins to be captured and examined during normal device operation, and permits an initial data pattern output at the device pins. Allows the external circuitry and board-level interconnections to be tested by forcing a test pattern at the output pins and capturing results at the input pins. Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data to pass synchronously through a selected device to adjacent devices during normal device operation. Selects the device IDCODE register and places it between TDI and TDO, allowing the device IDCODE to be serially shifted out of TDO. The device IDCODE for the EPC2 configuration device is shown below: 0000 0001000000000010 00001101110 1 Selects the USERCODE register and places it between TDI and TDO, allowing the USERCODE to be serially shifted out of TDO. The 32-bit USERCODE is a programmable user-defined pattern. These instructions are used when programming an EPC2 device via JTAG ports with a MasterBlaster, ByteBlaster MV, ByteBlaster, or BitBlaster download cable, or using a Jam STAPL File (.jam), Jam STAPL Byte-Code File (.jbc), or SVF File via an embedded processor. This function allows the user to initiate the APEX or FLEX configuration process by tying nINIT_CONF to the APEX or FLEX device(s) nCONFIG pin(s). After this instruction is updated, the nINIT_CONF pin is driven low. When the Initiate Configuration instruction is cleared, nINIT_CONF is released, which starts the APEX or FLEX device configuration. This instruction is used by the MAX+PLUS II software, Jam STAPL Files, and JBC Files.
IDCODE
USERCODE
ISP Instructions
INIT_CONF
f
For more information, see Application Note 39 (IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices). Figure 10 shows the timing requirements for the JTAG signals.
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Altera Corporation
Configuration Devices for SRAM-Based LUT Devices Data Sheet
Figure 10. EPC2 JTAG Waveforms
TMS
TDI
tJCP tJCH tJCL tJPSU tJPH
TCK
tJPZX tJPCO tJPXZ
TDO
tJSSU tJSH
Signal to Be Captured Signal to Be Driven
tJSZX
tJSCO
tJSXZ
Table 11 shows the timing parameters and values for configuration devices. Table 11. JTAG Timing Parameters & Values Symbol
tJCP tJCH tJCL tJPSU tJPH tJPCO tJPZX tJPXZ tJSSU tJSH tJSCO tJSZX tJSXZ TCK clock period TCK clock high time TCK clock low time JTAG port setup time JTAG port hold time JTAG port clock to output JTAG port high impedance to valid output JTAG port valid output to high impedance Capture register setup time Capture register hold time Update register clock to output Update register high-impedance to valid output Update register valid output to high impedance 20 45 25 25 25
Parameter
Min
100 50 50 20 45
Max
Unit
ns ns ns ns ns
25 25 25
ns ns ns ns ns ns ns ns
Operating Conditions
Altera Corporation
Tables 12 through 19 provide information on absolute maximum ratings, recommended operating conditions, DC operating conditions, and capacitance for configuration devices.
29
Configuration Devices for SRAM-based LUT Devices Data Sheet
f
For EPC4, EPC8, and EPC16 device operating conditions, refer to the Enhanced Configuration Devices (EPC4, EPC8, & EPC16) Data Sheet. Note (1) Conditions
With respect to ground (2) With respect to ground (2)
Table 12. Absolute Maximum Ratings Symbol
VCC VI IMAX IOUT PD T STG T AMB TJ
Parameter
Supply voltage DC input voltage DC VCC or ground current DC output current, per pin Power dissipation Storage temperature Ambient temperature Junction temperature No bias Under bias Under bias
Min
-2.0 -2.0 -25
Max
7.0 7.0 50 25 250
Unit
V V mA mA mW C C C
-65 -65
150 135 135
Table 13. Recommended Operating Conditions Symbol
VCC VI VO TA tR tF
Parameter
Supply voltage for 5.0-V operation Supply voltage for 3.3-V operation Input voltage Output voltage Operating temperature Input rise time Input fall time (3), (4) (3), (4)
Conditions
Min
3.0 (3.0) -0.3 0
Max
3.6 (3.6) V CC + 0.3 (5) V CC 70 85 20 20
Unit
V V V V C C ns ns
4.75 (4.50) 5.25 (5.50)
With respect to ground
For commercial use For industrial use
0 -40
Table 14. DC Operating Conditions Symbol
VIH VIL VOH
Parameter
High-level input voltage Low-level input voltage
Conditions
Min
2.0 -0.3 2.4 VCC - 0.2
Max
VCC + 0.3 (5) 0.8
Unit
V V V V
5.0-V mode high-level TTL output voltage IOH = -4 mA DC (6) 3.3-V mode high-level CMOS output voltage IOH = -0.1 mA DC (6) I OL = 4 mA DC (6) VI = VCC or ground VO = VCC or ground
VOL II IOZ
Low-level output voltage Input leakage current Tri-state output off-state current
0.4 -10 -10 10 10
V A A
30
Altera Corporation
Configuration Devices for SRAM-Based LUT Devices Data Sheet
Table 15. EPC1213, EPC1064 & EPC1064V Device ICC Supply Current Values Symbol
ICC0 ICC1
Parameter
VCC supply current (standby) VCC supply current (during configuration)
Conditions
Min
Typ
100 10
Max
200 50
Unit
A mA
Table 16. EPC2 Device ICC Supply Current Values Symbol
ICC0 ICC1
Parameter
VCC supply current (standby)
Conditions
VCC = 5.0 V or 3.3 V
Min
Typ
50 18
Max
100 50
Unit
A mA
VCC supply current (during configuration) VCC = 5.0 V or 3.3 V
Table 17. EPC1 Device ICC Supply Current Values Symbol
ICC0 ICC1
Parameter
VCC supply current (standby)
Conditions
Min
Typ
50 30 10
Max
100 50 16.5
Unit
A mA mA
VCC supply current (during configuration) VCC = 5.0 V VCC = 3.3 V
Table 18. EPC1441 Device ICC Supply Current Values Symbol
ICC0 ICC1 ICC1
Parameter
VCC supply current (standby)
Conditions
Min
Typ
30 15 5
Max
60 30 10
Unit
A mA mA
VCC supply current (during configuration) VCC = 5.0 V VCC supply current (during configuration) VCC = 3.3 V
Table 19. Capacitance Symbol
CIN COUT
Note (7) Conditions
VIN = 0 V, f = 1.0 MHz VOUT = 0 V, f = 1.0 MHz
Parameter
Input pin capacitance Output pin capacitance
Min
Max
10 10
Unit
pF pF
Notes to Tables 12 - 19:
(1) (2) (3) (4) (5) (6) (7) See the Operating Requirements for Altera Devices Data Sheet. The minimum DC input is -0.3 V. During transitions, the inputs may undershoot to -2.0 V or overshoot to 7.0 V for input currents less than 100 mA and periods shorter than 20 ns under no-load conditions. Numbers in parentheses are for industrial-temperature-range devices. Maximum VCC rise time is 100 ms. Certain EPC2 pins may be driven to 5.75 V when operated with a 3.3-V VCC. See Table 9 on page 26. The IOH parameter refers to high-level TTL or CMOS output current; the IOL parameter refers to low-level TTL or CMOS output current. Capacitance is sample-tested only.
Altera Corporation
31
Configuration Devices for SRAM-based LUT Devices Data Sheet
Tables 20 through 24 show the device configuration parameters for APEX II, APEX 20K, Mercury, ACEX 1K, or FLEX devices. Table 20. ACEX 1K, FLEX 10K & FLEX 6000 Device Configuration Parameters Using EPC2 Devices at 5.0-V Symbol
tCE tOEZX tCO tMCH tMCL fCK tSCH tSCL tCASC tCCA fCDOE tOEC tNRCAS tNRR
Parameter
OE high to first clock delay OE high to data output enabled DCLK to data out delay DCLK high time for the first device in the configuration chain DCLK low time for the first device in the configuration chain Clock frequency DCLK high time for subsequent devices DCLK low time for subsequent devices CLK rising edge to nCASC nCS to nCASC cascade delay CLK to data enable/disable OE low to CLK disable delay OE low (reset) to nCASC delay OE low time (reset) minimum
Conditions
Min
Typ
Max
200 50 20
Unit
ns ns ns ns ns MHz ns ns
30 30 6.7 30 30
50 50 10
75 75 16.7
20 10 20 20 25 100
ns ns ns ns ns ns
Table 21. ACEX 1K, APEX 20K, APEX II, FLEX 10K & Mercury Device Configuration Parameters Using EPC2 Devices at 3.3-V Symbol
tCE tOEZX tCO tMCH tMCL fCK tSCH tSCL tCASC tCCA fCDOE tOEC tNRCAS tNRR
Parameter
OE high to first clock delay OE high to data output enabled DCLK to data out delay DCLK high time for the first device in the configuration chain DCLK low time for the first device in the configuration chain Clock frequency DCLK high time for subsequent devices DCLK low time for subsequent devices CLK rising edge to nCASC nCS to nCASC cascade delay CLK to data enable/disable OE low to CLK disable delay OE low (reset) to nCASC delay OE low time (reset) minimum
Conditions
Min
Typ
Max
300 80 30
Unit
ns ns ns ns ns MHz ns ns
40 40 5 40 40
65 65 7.7
100 100 12.5
25 15 30 30 30 100
ns ns ns ns ns ns
32
Altera Corporation
Configuration Devices for SRAM-Based LUT Devices Data Sheet
Table 22. ACEX 1K, FLEX 10K & FLEX 6000 Device Configuration Parameters Using EPC1 & EPC1441 Devices at 5.0-V Symbol
tCE tOEZX tCO tMCH tMCL fCK tSCH tSCL tCASC tCCA fCDOE tOEC tNRCAS tNRR
Parameter
OE high to first clock delay OE high to data output enabled DCLK to data out delay DCLK high time for the first device in the configuration chain DCLK low time for the first device in the configuration chain Clock frequency DCLK high time for subsequent devices DCLK low time for subsequent devices CLK rising edge to nCASC nCS to nCASC cascade delay CLK to data enable/disable OE low to CLK disable delay OE low (reset) to nCASC delay OE low time (reset) minimum
Conditions
Min
Typ
Max
200 50 20
Unit
ns ns ns ns ns MHz ns ns
30 30 6.7 30 30
50 50 10
75 75 16.7
20 10 20 20 25 100
ns ns ns ns ns ns
Table 23. ACEX 1K, FLEX 10K & FLEX 6000 Device Configuration Parameters Using EPC1 & EPC1441 Devices at 3.3-V Symbol
tCE tOEZX tCO tMCH tMCL fCK tSCH tSCL tCASC tCCA fCDOE tOEC tNRCAS tNRR
Parameter
OE high to first clock delay OE high to data output enabled DCLK to data out delay DCLK high time for the first device in the configuration chain DCLK low time for the first device in the configuration chain Clock frequency DCLK high time for subsequent devices DCLK low time for subsequent devices CLK rising edge to nCASC nCS to nCASC cascade delay CLK to data enable/disable OE low to CLK disable delay OE low (reset) to nCASC delay OE low time (reset) minimum
Conditions
Min
Typ
Max
300 80 30
Unit
ns ns ns ns ns MHz ns ns
50 50 2 50 50
125 125 4
250 250 10
25 15 30 30 30 100
ns ns ns ns ns ns
Altera Corporation
33
Configuration Devices for SRAM-based LUT Devices Data Sheet
Table 24. FLEX 8000 Device Configuration Parameters Using EPC1, EPC1441, EPC1213, EPC1064 & EPC1064V Devices Symbol Parameter Conditions EPC1064V EPC1064 EPC1213 EPC1 Unit EPC1441
Min Max Min Max Min Max
tOEZX tCSZX tCSXZ tCSS tCSH tDSU tDH tCO tCK fCK tCL tCH tXZ tOEW tCASC tCKXZ tCEOUT OE high to DATA output enabled nCS low to DATA output enabled nCS high to DATA output disabled nCS low setup time to first DCLK rising edge nCS low hold time after DCLK rising edge Data setup time before rising edge on DCLK Data hold time after rising edge on DCLK DCLK to DATA out delay Clock period Clock frequency DCLK low time DCLK high time OE low or nCS high to DATA output disabled OE pulse width to guarantee counter reset Last DCLK + 1 to nCASC low delay Last DCLK + 1 to DATA tri-state delay nCS high to nCASC high delay 150 90 75 150 120 120 75 100 60 50 100 240 4 80 80 50 100 50 50 100 150 0 75 0 100 160 6 50 50 50 75 75 75 100 0 50 0 75 100 8 50 50 50 50 0 50 0 75 50 50 50 ns ns ns ns ns ns ns ns ns MHz ns ns ns ns ns ns ns
Revision History
The information contained in the Configuration Devices for SRAM-Based LUT Devices Data Sheet version 12.2 supersedes information published in pervious versions. The following changes were made to the Configuration Devices for SRAM-Based LUT Devices Data Sheet version 12.2:
Version 12.2

Corrected the APEX 20KE voltate in Table 2 to 1.8 V. Updated Figure 5.
Version 12.1

Updated Table 2. Updated notes to Figures 4, 5, and 6. Added APEX 20KE device diagrams to Figures 4 and 6.
34
Altera Corporation
Configuration Devices for SRAM-Based LUT Devices Data Sheet
Notes:
Altera Corporation
35
Configuration Devices for SRAM-Based LUT Devices Data Sheet
(R)
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Copyright (c) 2002 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, mask work rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
36
Altera Corporation

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